Topological Optimization of Multiple-Level Array Logic

A generalized topological optimization tool for array-based layout styles is presented. This tool can be used for automated layout synthesis of logic networks in a variety of technologies and design styles, including static CMOS, static NMOS and dynamic MOS domino structures. Results obtained compare favorably with technology and design-style-specific synthesis systems. The topological optimization tool is a generalized array optimizer which can be used for the multiple constrained folding of programmable logic array, gate matrix, Weinberger array, multilevel matrix, and storage/logic array structures. The optimizer uses simulated-annealing-based algorithms and performs as well as or better than existing specialized PLA folding programs and gate matrix folders. The different layout style alternatives allow area-efficient synthesis of logic circuits in various technologies. Layout for sequential logic in the form of storage/logic arrays has been automated for the first time. A multiprocessor implementation of the simulated-annealing-based algorithms for generalized array optimization has been developed on the Sequent Balance 8000 multiprocessor. Dynamic windowing and dynamic partitioning techniques have resulted in an efficient parallel implementation of simulated annealing.