DocumentCode :
915538
Title :
Testability-Driven Random Test-Pattern Generation
Author :
Lisanke, Robert ; Brglez, Franc ; de Geus, A.J. ; Gregory, David
Author_Institution :
Microelectronics Center of North Carolina, Research Triangle Park, NC, USA
Volume :
6
Issue :
6
fYear :
1987
fDate :
11/1/1987 12:00:00 AM
Firstpage :
1082
Lastpage :
1087
Abstract :
This paper presents ESPRIT, an automatic test pattern generation (ATPG) system for testing single stuck-at faults in combinational logic. ESPRIT generates test patterns by performing fault simulation on random patterns derived from nonuniformly distributed input signal probabilities. The system computes input signal probabilities that minimize a testability cost function. Using ESPRIT, we have observed orders-of-magnitude reduction in the number of random trials required to obtain a given fault coverage.
Keywords :
Automatic logic units; Automatic test pattern generation; Automatic testing; Computational modeling; Cost function; Logic testing; Performance evaluation; Signal generators; System testing; Test pattern generators;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.1987.1270348
Filename :
1270348
Link To Document :
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