A self-aligned pocket implantation (SPI) technology for 0.2- mu m dual-gate CMOS

Author

Hori, Atsushi ; Segawa, Mizuki ; Shimomura, Hiroshi ; Kameyama, Shuuich

Author_Institution

Matsushita Electr. Ind. Co. Ltd., Osaka, Japan

Volume

13

Issue

4

fYear

1992

fDate

4/1/1992 12:00:00 AM

Firstpage

174

Lastpage

176

Abstract

The self-aligned pocket implantation (SPI) technology developed features a localized pocket implantation using a gate electrode and TiSi/sub 2/ films as self-aligned masks. This process provides high punchthrough resistance and high current driving capability while suppressing the impurity concentration in the twin well. The drain junction capacitance is decreased by 30% for N-MOSFETs and by 49% for P-MOSFETs, compared to conventional LDD devices. It is found that a dual-gate CMOS device fabricated by the SPI technology achieves high circuit performance.<>

Keywords

CMOS integrated circuits; insulated gate field effect transistors; integrated circuit technology; ion implantation; 0.2 micron; N-MOSFETs; P-MOSFETs; TiSi/sub 2/ films; drain junction capacitance; dual-gate CMOS; gate electrode; high current driving capability; high punchthrough resistance; impurity concentration suppression; localized pocket implantation; self-aligned pocket implantation; Boron; CMOS technology; Circuit optimization; Doping profiles; Electrodes; Impurities; MOSFET circuits; Parasitic capacitance; Semiconductor films; Substrates;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.145011

Filename

145011