Title :
Economical realisation of asynchronous sequential circuits using random-access memories
Author :
Thomas, Babu ; Chandrasekharan, P.C.
Author_Institution :
College of Engineering, Department of Electrical Electronics & Communication Engineering, Madras, India
fDate :
5/1/1981 12:00:00 AM
Abstract :
This paper shows that by taking advantage of a fairly uniform delay distribution in semiconductor random-access memories (ROMs and read-write memories in integrated circuit form) it is possible to realise asynchronous sequential circuits (ASCs) economically. It is shown that the ASC so designed will function without fault, in spite of the presence of races and essential hazards in the ASC.
Keywords :
asynchronous sequential logic; logic circuits; logic design; random-access storage; ASC; asynchronous sequential circuits; hazards; races; random-access memories;
Journal_Title :
Computers and Digital Techniques, IEE Proceedings E
DOI :
10.1049/ip-e.1981.0025
