DocumentCode :
917453
Title :
Guest Editors´ Introduction: GALS Design and Validation
Author :
Kishinevsky, Mike ; Shukla, Sandeep K. ; Stevens, Kenneth S.
Author_Institution :
Intel
Volume :
24
Issue :
5
fYear :
2007
Firstpage :
414
Lastpage :
416
Abstract :
Globally asynchronous, locally synchronous (GALS) design has grown in popularity in both academia and industry. Breaking the synchrony assumption in digital design is often unsettling for designers, and to alleviate the difficulty, researchers in EDA have been proposing various GALS-based solutions. However, the tools, verification techniques, and testing methodologies for asynchronous designs are not as widespread as for synchronous digital design, leading to the hitherto limited usage of GALS design approaches. This special issue introduces some of the basic issues of GALS design and validation in the hardware domain. The hope is that this special issue will generate more interest by researchers and industry practitioners in creating design tools, techniques, and validation methodologies for GALS design.
Keywords :
Circuit testing; Clocks; Costs; Delay; Design methodology; Electronic design automation and methodology; Energy consumption; Frequency synchronization; Manufacturing processes; Semiconductor device manufacture; asynchronous; design; synchronous; validation;
fLanguage :
English
Journal_Title :
Design & Test of Computers, IEEE
Publisher :
ieee
ISSN :
0740-7475
Type :
jour
DOI :
10.1109/MDT.2007.166
Filename :
4338459
Link To Document :
بازگشت