Title :
A GALS Infrastructure for a Massively Parallel Multiprocessor
Author :
Plana, Luis A. ; Furber, Steve B. ; Temple, Steve ; Khan, Mukaram ; Shi, Yebin ; Wu, Jian ; Yang, Shufan
Abstract :
This case study focuses on a massively parallel multiprocessor for real-time simulation of billions of neurons. Every node of the design comprises 20 ARM9 cores, a memory interface, a multicast router, and two NoC structures for communicating between internal cores and the environment. The NoCs are asynchronous; the cores and RAM interfaces are synchronous. This GALS approach decouples clocking concerns for different parts of the die, leading to greater power efficiency.
Keywords :
asynchronous circuits; multiprocessing systems; network-on-chip; neural nets; random-access storage; real-time systems; ARM9 cores; GALS infrastructure; NoC structures; RAM interfaces; massively parallel multiprocessor; memory interface; multicast router; neurons; real-time simulation; Bandwidth; Clocks; Network-on-a-chip; Neurons; Performance evaluation; Power system modeling; Routing; SDRAM; Testing; Timing; GALS; Spinnaker; massively parallel multiprocessor; neural modeling; self-timed interconnect;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2007.149
