DocumentCode :
917558
Title :
Module relocation to obtain feasible constrained floorplans
Author :
Feng, Yan ; Mehta, Dinesh P.
Author_Institution :
Dept. of Math. & Comput. Sci., Colorado Sch. of Mines, Golden, CO, USA
Volume :
25
Issue :
5
fYear :
2006
fDate :
5/1/2006 12:00:00 AM
Firstpage :
856
Lastpage :
866
Abstract :
This paper considers the general problem of relocating modules to convert infeasible constrained floorplanner inputs into feasible ones. This is accomplished by placing modules in locations that attempt to minimize the standard deviation of module densities. Efficient geometric algorithms are developed and shown to be successful in obtaining feasible inputs. Experimental results examine the tradeoffs between achieving a good redistribution of density on one hand and minimizing the increase in wire length and the displacement of modules on the other.
Keywords :
circuit layout; computational geometry; geometric programming; modules; computational geometry; constrained floorplans; density redistribution; feasible floorplans; geometric algorithms; incremental floorplanning; module densities; module relocation; wire length; Computational geometry; Computer science; Context modeling; Design methodology; Packaging; Shape; Simulated annealing; Testing; Wire; Algorithm; computational geometry; incremental floorplanning; placement; standard deviation;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2005.855981
Filename :
1624518
Link To Document :
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