Title :
A comparison of VLSI architecture of finite field multipliers using dual, normal, or standard bases
Author :
Hsu, I.S. ; Truong, T.K. ; Deutsch, L.J. ; Reed, I.S.
Author_Institution :
Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
fDate :
6/1/1988 12:00:00 AM
Abstract :
Three different finite-field multipliers are presented: (1) a dual-basis multiplier due to E.R. Berlekamp (1982); the Massey-Omura normal basis multiplier; and (3) the Scott-Tavares-Peppard standard basis multiplier. These algorithms are chosen because each has its own distinct features that apply most suitably in particular areas. They are implemented on silicon chips with NMOS technology so that the multiplier most desirable for VLSI implementation can readily be ascertained
Keywords :
VLSI; field effect integrated circuits; multiplying circuits; Massey-Omura normal basis multiplier; NMOS technology; Scott-Tavares-Peppard standard basis multiplier; VLSI architecture; dual-basis multiplier; finite field multipliers; Computer architecture; Data structures; Databases; Delay; Dictionaries; Galois fields; Parallel processing; Pipelines; Tree data structures; Very large scale integration;
Journal_Title :
Computers, IEEE Transactions on
