Title :
A High-Performance and Energy-Efficient TCAM Design for IP-Address Lookup
Author_Institution :
Dept. of Comput. Sci. & Eng., Nat. Chung Hsing Univ., Taichung
fDate :
6/1/2009 12:00:00 AM
Abstract :
In this brief, we propose a two-level don´t-care gating (DCG) scheme that aims to reduce the ternary content-addressable memory (TCAM) power dissipated in the search-line switching activity. By exploiting the vertically continuous ldquodon´t-carerdquo feature, the two-level DCG scheme can largely reduce the average search-line power consumption during a switch pattern. In addition, we also use the search enable technique to eliminate the unnecessary search-line switching activity in the quiet pattern. By reducing both the search-line switching activity and average switching power, the proposed design can minimize the TCAM search-line power consumption. For a 128 times 32 TCAM, the best configuration we examined shows that when the first-level and second-level gating granularities are 16 and 8, respectively, with a 9% search performance improvement, the two-level DCG scheme can achieve 70% search-line energy reduction.
Keywords :
SRAM chips; logic gates; low-power electronics; IP-address lookup; first-level gating granularities; search-line power consumption; search-line switching activity; second-level gating granularities; six-transistor static random access memory cell; switch pattern; ternary content-addressable memory; two-level don´t-care gating scheme; Forwarding table; low-power design; router; search line (SL); ternary content addressable memory (TCAM);
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2009.2020935