Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires

This letter demonstrates a vertical silicon-nanowire (SiNW)-based tunneling field-effect transistor (TFET) using CMOS-compatible technology. With a Si p⁺-i- n⁺ tunneling junction, the TFET with a gate length of ~ 200 nm exhibits good subthreshold swing of ~ 70 mV/dec, superior drain-induced-barrier-lowering of ~ 17 mV/V, and excellent I _on - I _off ratio of ~ 10⁷ with a low I _off ( ~ 7 pA/mum). The obtained 53 muA/mum I _on can be further enhanced with heterostructures at the tunneling interface. The vertical SiNW-based TFET is proposed to be an excellent candidate for ultralow power and high-density applications.