Title :
Performance enhancement of partially and fully depleted strained-SOI MOSFETs
Author :
Numata, Toshinori ; Irisawa, Toshifumi ; Tezuka, Tsutomu ; Koga, Junji ; Hirashita, Norio ; Usuda, Koji ; Toyoda, Eiji ; Miyamura, Yoshiji ; Tanabe, Akihito ; Sugiyama, Naoharu ; Takagi, Shin-ichi
Author_Institution :
Assoc. of Super-Adv. Electron. Technol., Kawasaki, Japan
fDate :
5/1/2006 12:00:00 AM
Abstract :
The authors have developed short-channel strained-silicon-on-insulator (strained-SOI) MOSFETs on silicon-germanium (SiGe)-on-insulator (SGOI) substrates fabricated by the Ge condensation technique. 35-nm-gate-length strained-SOI MOSFETs were successfully fabricated. The strain in Si channel is still maintained for the gate length of 35 nm. The performance enhancement of over 15% was obtained in 70-nm-gate-length strained-SOI n-MOSFETs. Fully depleted strained-SOI MOSFETs with back gate were successfully fabricated on SGOI substrate with SiGe layers as thin as 25 nm. The back-gate bias control successfully operated and the higher current drive was obtained by a combination of the low doping channel and the back-gate control.
Keywords :
Ge-Si alloys; MOSFET; semiconductor doping; silicon-on-insulator; 35 nm; 70 nm; SGOI substrates; SiGe; back-gate bias control; low doping channel; short-channel SOI MOSFET; silicon on insulator; silicon-germanium; strained-SOI MOSFET; Capacitive sensors; Doping; Germanium silicon alloys; MOSFET circuits; Silicon germanium; Space technology; Stress; Substrates; Threshold voltage; Voltage control; MOSFETs; silicon–germanium (SiGe); silicon-on-insulator (SOI); strained-silicon (strained-Si);
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2006.871871
