Hardware efficient decoding of LDPC codes using partial-min algorithms

In this paper, the partial-min algorithms are proposed for updating the check node messages in decoding low-density parity-check (LDPC) codes. The proposed methods can achieve a good performance-versus-complexity tradeoff by reducing both the check node processor complexity and the decoder memory requirements. Float-point and fixed-point simulation results show that a near optimum performance can be maintained. The architecture of a check node processor implementing the partial-min algorithms is also presented. The hardware expense especially the memory requirement is analyzed and compared with normal decoding architectures