Wave digital filter hardware structure

A large amount of literature has been published during the last decade on the design of digital filter structures with desirable attributes, such as low round off noise, simple coefficients or ease of implementation. In this paper, the hardware implementation of a structure based on a classical doubly-terminated distributed filter prototype is discussed. This structure has a prarticularly simple form as it is a cascade of identical 1st-order networks. The paper describes a programmable logic design centred on a high-speed bipolar LSI multiplier chip. It is shown that a complete 6th degree wave digital filter with analogue I/O can be implemented on a single S-100 printed-circuit board, and further that the filter can operate at a maximum sampling rate of around 150 kHs. The filter coefficients can be change in the controll program which is also stored in PROM.