Physically based quantum-mechanical compact model of MOS devices substrate-injected tunneling current through ultrathin (EOT ∼ 1 nm) SiO2 and high-κ gate stacks

Building on a previously presented compact gate capacitance (C_g-V_g) model, a computationally efficient and accurate physically based compact model of gate substrate-injected tunneling current (I_g-V_g) is provided for both ultrathin SiO₂ and high-dielectric constant (high-κ) gate stacks of equivalent oxide thickness (EOT) down to ∼ 1 nm. Direct and Fowler-Nordheim tunneling from multiple discrete subbands in the strong inversion layer are addressed. Subband energies in the presence of wave function penetration into the gate dielectric, charge distributions among the subbands subject to Fermi-Dirac statistics, and the barrier potential are provided from the compact C_g-V_g model. A modified version of the conventional Wentzel-Kramer-Brillouin approximation allows for the effects of the abrupt material interfaces and nonparabolicities in complex band structures of the individual dielectrics on the tunneling current. This compact model produces simulation results comparable to those obtained via computationally intense self-consistent Poisson-Schrödinger simulators with the same MOS devices structures and material parameters for 1-nm EOTs of SiO₂ and high-κ/SiO₂ gate stacks on (100) Si, respectively. Comparisons to experimental data for MOS devices with metal and polysilicon gates, ultrathin dielectrics of SiO₂, Si₃N₄, and high-κ (e.g., HfO₂) gate stacks on (100) Si with EOTs down to ∼ 1-nm show excellent agreement.