Characterization of mixed-signal properties of MOSFETs with high-k (SiON/HfSiON/TaN) gate stacks

The correlation between the stoichiometry of HfSiON gate dielectrics and mixed-signal properties of low-power MOSFETs is investigated. MOSFETs with gate length L down to 100 nm were fabricated in a conventional fabrication flow with a thermal budget of 1000°C. The equivalent oxide thickness values of the gate stacks ranged from 12.0 to 14.4 Å. The inversion thickness t_ox^inv ranged between 16.2 and 18.9 Å. Accumulation leakage current density at V_g=V_fb-1 V ranged from 3.1×10^-3 to 3.9×10^-2 A·cm^-2, corresponding to a leakage reduction of around 1000 times compared with that of SiON/TaN. The inversion leakage current density at V_g=V_t+0.7 V was found to be between 0.18 and 0.66 A·cm^-2, i.e., 20 times lower than that of SiON/TaN. The threshold voltage instability (ΔV_t) of the high-k gate stacks was found to be below 10 mV, corresponding to a (bulk) oxide trap density N_ot<3×10¹⁰ cm^-2. Normalized input-referred gate noise spectra S_vg showed minor dependence on the Hf content of the gate dielectric. This is attributed to the fact that the main sources for the low-frequency (LF) 1/f noise are defects located at the interfaces rather than bulk defects in the gate dielectric. Moderate high- and low-field mobilities of 50%-70% of a SiON/TaN reference device were found in MOSFETs with Hf-based gate dielectric. Of the investigated layers, stoichiometric (55% Hf) and Hf-rich (70% Hf) silicates on SiO₂ interface show the best compromise in terms of gate leakage reduction, threshold voltage instability, LF noise, drive current, and analog voltage gain. For an HfSiON silicate dielectric layer with 70% Hf and SiO₂ interface, a low-field peak electron mobility μ_eff=148 cm²/V·s, an oxide trap density N_ot<1.4×10¹⁰ cm^-2, and a drive current I_ON=459 μA/μm at I_OFF=9 pA/μm were found. The analog voltage gain A_v of a MOSFET with this gate dielectric and W/L=1/0.45 was found to be A_v=121. To meet specifications for mixed-signal properties, optimization of dopant engineering along with tuning of the- gate stack properties is required to improve the performance of high-k-based MOSFETs.