Title :
Removal of Negative-Bias-Illumination-Stress Instability in Amorphous-InGaZnO Thin-Film Transistors by Top-Gate Offset Structure
Author :
Suhui Lee ; Mativenga, Mallory ; Jin Jang
Author_Institution :
Dept. of Inf. Display, Kyung Hee Univ., Seoul, South Korea
Abstract :
A highly stable, dual-gate (DG) amorphous, indium-gallium-zinc oxide (a-IGZO) thin-film transistor (TFT) with an offset top-gate (TG) is reported. Given that both gates are opaque and electrically tied together, the TG functions as a lightshield and drain-current (IDS) enhancer as synchronized gate-voltage (VGS) sweep induces bulk-accumulation (BA) at positive voltages. It is demonstrated here that regardless of the offsets between the TG and source/drain electrode, this BA a-IGZO TFT is immune to negative bias and light-illumination stress (NBIS) when the TG covers at least 50% of the channel region. Therefore, high performance BA a-IGZO TFTs that are also immune to NBIS can be designed without introducing additional parasitic capacitance that occurs when the TG overlaps the source and/or drain electrode(s).
Keywords :
accumulation layers; amorphous semiconductors; circuit stability; gallium compounds; indium compounds; thin film transistors; zinc compounds; InGaZnO; NBIS; bulk-accumulation; drain-current enhancer; dual-gate a-IGZO thin-film transistor; dual-gate amorphous indium-gallium-zinc oxide TFT; light-illumination stress; lightshield; negative bias; offset top-gate; source-drain electrode; synchronized gate-voltage sweep; Barium; Electrodes; Lighting; Logic gates; Stress; Thin film transistors; a-IGZO; bulk accumulation; dual gate; negative bias illumination stress (NBIS); thin film transistor (TFT); thin film transistor (TFT).;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2014.2333014
