DocumentCode :
920228
Title :
Initialization-Based Test Pattern Generation for Asynchronous Circuits
Author :
Efthymiou, Aristides
Author_Institution :
Sch. of Inf., Univ. of Edinburgh, Edinburgh, UK
Volume :
18
Issue :
4
fYear :
2010
fDate :
4/1/2010 12:00:00 AM
Firstpage :
591
Lastpage :
601
Abstract :
A novel test pattern generation method for asynchronous circuits is described and evaluated in detail. The method combines conventional pattern generation with hazard-free state initialization. Any type of asynchronous circuit can be processed, and all stuck-at faults, even those inside state-holding elements, such as C-elements, are considered. The results on some of the largest benchmarks ever used for asynchronous circuit testing show fault coverage on the order of 99% with no area overhead for (quasi-)delay-insensitive datapath circuits.
Keywords :
asynchronous circuits; automatic test pattern generation; fault diagnosis; asynchronous circuits; hazard-free state initialization; initialization-based test pattern generation; pattern generation; quasidelay-insensitive datapath circuits; state-holding elements; Asynchronous circuits; automatic test pattern generation (ATPG); sequential initialization; stuck-at fault testing;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2009.2013470
Filename :
4982920
Link To Document :
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