Title :
Pipeline array for square-root extraction
Author_Institution :
University of Waterloo, Department of Electrical Engineering, Faculty of Engineering, Waterloo, Canada
Abstract :
Pipelining an arithmetic process is a well known technique for improving the computation speed of the arithmetic algorithm. In the letter is proposed a pipeline version of the array for the extraction of square roots of binary numbers. It is shown that a significant speed improvement (on a throughout basis) can result by this modification of the conventional logic arrays.
Keywords :
cellular arrays; digital arithmetic; logic circuits; arithmetic process pipelining; cellular arrays; conventional logic arrays; square root extraction;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19730003
