Title :
A 2.5-Gb/s 15-mW clock recovery circuit
Author_Institution :
AT&T Bell Labs., Holmdel, NJ, USA
fDate :
4/1/1996 12:00:00 AM
Abstract :
This paper describes the design of a 2.5-Gb/s 15-mW clock recovery circuit based on the quadricorrelator architecture. Employing both phase and frequency detection, the circuit combines high-speed operations such as differentiation, full-wave rectification, and mixing in one stage to lower the power dissipation. In addition, a two-stage voltage-controlled oscillator is utilized that incorporates both phase shift elements to provide a wide tuning range and isolation techniques to suppress the feedthrough due to input data transitions. Fabricated in a 20-GHz 1-μm BiCMOS technology, the circuit exhibits an rms jitter of 9.5 ps and a capture range of 300 MHz
Keywords :
BiCMOS digital integrated circuits; clocks; recovery; 1 micron; 15 mW; 2.5 Gbit/s; 20 GHz; BiCMOS technology; RMS jitter; capture range; clock recovery circuit; data transition feedthrough; design; differentiation; frequency detection; full-wave rectification; high-speed operations; isolation; low power operation; mixing; phase detection; phase shift elements; quadricorrelator architecture; tuning; two-stage voltage-controlled oscillator; BiCMOS integrated circuits; Circuit optimization; Clocks; Isolation technology; Jitter; Phase detection; Phase frequency detector; Power dissipation; Tuning; Voltage-controlled oscillators;
Journal_Title :
Solid-State Circuits, IEEE Journal of
