Driving source-line cell architecture for sub-1-V high-speed low-power applications

Author

Mizuno, Hiroyuki ; Nagano, Takahiro

Author_Institution

Central Res. Lab., Hitachi Ltd., Tokyo, Japan

Volume

31

Issue

4

fYear

1996

fDate

4/1/1996 12:00:00 AM

Firstpage

552

Lastpage

557

Abstract

A novel SRAM cell architecture for sub-1-V high-speed operation is proposed that uses neither low-V_th MOSFETs nor modified cell layout patterns. A source-line, connected to the source terminals of the driver MOSFETs is controlled so that it is negative and floating in the read and write cycles, respectively. This improved the bit-line access time by 1/4-1/2 at supply voltages of 0.5-1.0 V. Limiting the bit-line swing reduces by 1/10 the writing power needed to charge them and allows faster write-recovery, as well. The achievability of low-power 100-MHz operation over a wide range of supply voltages is demonstrated

Keywords

CMOS memory circuits; SRAM chips; memory architecture; 0.5 to 1 V; 100 MHz; SRAM cell architecture; bit-line access time; driver MOSFET; driving source-line cell architecture; high-speed operation; low-power applications; static RAM; DSL; Large scale integration; Logic devices; Low voltage; MOSFETs; Power dissipation; Random access memory; Switching circuits; Threshold voltage; Throughput; Voltage; Writing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.499732

Filename

499732