Title :
A 286 mm2 256 Mb DRAM with ×32 both-ends DQ
Author :
Watanabe, Yohji ; Wong, Hing ; Kirihata, Toshiaki ; Kato, Daisuke ; DeBrosse, John K. ; Hara, Takahiko ; Yoshida, Munehiro ; Mukai, Hideo ; Quader, Khandker N. ; Nagai, Takeshi ; Poechmueller, Peter ; Pfefferl, Peter ; Wordeman, Matthew R. ; Fujii, Shuso
Author_Institution :
Semicond. Res. & Dev. Centre, IBM Corp., Hopewell Junction, NY, USA
fDate :
4/1/1996 12:00:00 AM
Abstract :
This paper describes a 256 Mb DRAM chip architecture which provides up to ×32 wide organization. In order to minimize the die size, three new techniques: an exchangeable hierarchical data line structure, an irregular sense amp layout, and a split address bus with local redrive scheme in the both-ends DQ were introduced. A chip has been developed based on the architecture with 0.25 μm CMOS technology. The chip measures 13.25 mm×21.55 mm, which is the smallest 256 Mb DRAM ever reported. A row address strobe (RAS) access time of 26 ns was obtained under 2.8 V power supply and 85°C. In addition, a 100 MHz×32 page mode operation, namely 400 M byte/s data rate, in the standard extended data output (EDO) cycle has been successfully demonstrated
Keywords :
CMOS memory circuits; DRAM chips; 100 MHz; 2.8 V; 256 Mbit; 26 ns; 400 Mbyte/s; 85 C; CMOS technology; DRAM chip architecture; both-ends DQ; dynamic RAM; exchangeable hierarchical data line structure; extended data output cycle; irregular sense amp layout; local redrive scheme; page mode operation; split address bus; Artificial intelligence; CMOS technology; Circuits; Decoding; Helium; Microcomputers; Microprocessors; Power supplies; Random access memory; Research and development; Semiconductor device measurement;
Journal_Title :
Solid-State Circuits, IEEE Journal of
