Title :
Tolerance design via cost minimisation
Author_Institution :
Imperial College of Science & Technology, Department of Electrical Engineering, London, UK
fDate :
8/1/1982 12:00:00 AM
Abstract :
A new method is described for the tolerance design of circuits, via minimisation of a cost function of the yield and tolerances. This problem is decomposed into the simpler problems of design centring with fixed tolerances, and tolerance assignment by efficient nonlinear optimisation based on a nonlinear approximation of the yield/tolerance dependence. Two algorithms are proposed, and their performance is evaluated on numerical examples.
Keywords :
minimisation; network synthesis; circuit design; cost minimisation; design centering; efficient nonlinear optimisation; network synthesis; tolerance assignment; tolerance design; yield; yield/tolerance dependence;
Journal_Title :
Electronic Circuits and Systems, IEE Proceedings G
DOI :
10.1049/ip-g-1:19820028
