DocumentCode :
922276
Title :
As good as gold [circuit design]
Author :
Blackett, R. Kent
Author_Institution :
Chrysalis Symbolic Design Inc., North Billerica, MA, USA
Volume :
33
Issue :
6
fYear :
1996
fDate :
6/1/1996 12:00:00 AM
Firstpage :
68
Lastpage :
71
Abstract :
Simulation is a natural outgrowth of the hardware breadboard that preceded engineering workstations and commercial design automation tools. For the breadboard, simulation substitutes software: a netlist or a model in a hardware description language (HDL) represents the design, then the simulator automatically applies stimuli to the model´s inputs and captures the response of the model´s outputs. Using such a system, designers show that a design meets functional requirements by trying many different operational scenarios. However, as designs grow larger, the time required to simulate each function grows exponentially. The paper discusses the use of formal verification approaches for logic design
Keywords :
circuit analysis computing; digital simulation; formal verification; hardware description languages; logic CAD; circuit design; circuit simulation; design automation tools; engineering workstations; formal verification; functional requirements; hardware description language; logic design; model output response; Circuit simulation; Circuit testing; Formal verification; Gold; Integrated circuit testing; Logic circuits; Logic design; Logic devices; Logic testing; Signal design;
fLanguage :
English
Journal_Title :
Spectrum, IEEE
Publisher :
ieee
ISSN :
0018-9235
Type :
jour
DOI :
10.1109/6.499955
Filename :
499955
Link To Document :
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