Linear digital phase-locked loops using integrators in a pulse frequency-modulation system

The conventional digital phase-locked loop (DPLL) has a number of problems which need to be solved: the pull-in and lock ranges are very restricted by the phase detector and are dependent on the noise bandwidth, and their operation is not linear. In the paper, DPLLs free from such disadvantages are proposed. These DPLLs are realised by a new method, i.e. by use of integrators in a pulse frequency-modulation system, and the higher-order DPLL is systematically designed by controlling the free-running frequency of one VCO with the error of the other DPLLs. The operation of the DPLL is similar to that of an analogue PLL (APLL). However, the former operates linearly in a wider region than does the latter; unlike the APLL, the pull-in and lock ranges of the first-order and imperfect second-order DPLL are the same as those of the perfect second- order APLL in the range from zero to almost the maximum frequency of the VCO and are independent of the noise bandwidth. Excellent agreement is obtained between theory and experiments.