Title :
Optimizing power in ASIC behavioral synthesis
Author :
Martin, Raul San ; Knight, John P.
Author_Institution :
Nortel Technol., Ottawa, Ont., Canada
Abstract :
Attacking power consumption at the behavioral level exploits an application´s inherent parallelism to maintain performance while compensating for slower, less power-hungry operators. The authors´ method and tool optimize and evaluate the effects of power-saving strategies on performance and silicon area
Keywords :
application specific integrated circuits; circuit CAD; power consumption; ASIC behavioral synthesis; performance; power consumption; power optimisation; power-saving strategies; silicon area; Adders; Application specific integrated circuits; Arithmetic; CMOS logic circuits; Clocks; Delay effects; Minimization; Scheduling algorithm; Silicon; Voltage;
Journal_Title :
Design & Test of Computers, IEEE
