Area-efficient architectures for the Viterbi algorithm. I. Theory

Author

Shung, C. Bernard ; Lin, Horng-Dar ; Cypher, Robert ; Siegel, Paul H. ; Thapar, Hemant K.

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

41

Issue

4

fYear

1993

fDate

4/1/1993 12:00:00 AM

Firstpage

636

Lastpage

644

Abstract

In the state-parallel implementation of the Viterbi algorithm, one add-compare-select (ACS) unit is devoted to each state in the treillis. A systematic approach to partitioning, scheduling, and mapping N trellis states to P ACSs, where N>P , is presented here. The area saving of this architecture comes from the reduced number of ACSs and interconnection wires. The design of the ACS, path metric storage, and routing network is discussed in detail. The proposed architecture creates internal parallelism due to the ACS sharing, which can be exploited to increase the throughput rate by pipelining. Consequently, the architecture offers a favorable (smaller) area-time product, compared to the state-parallel implementation

Keywords

parallel architectures; Viterbi algorithm; add compare select unit; area efficient architectures; area-time product; decoding; parallel architecture; partitioning; path metric storage; pipelining; routing network; scheduling; state-parallel implementation; throughput rate; trellis states; Helium; Intersymbol interference; Maximum likelihood decoding; Pipeline processing; Routing; Signal processing algorithms; Speech recognition; Throughput; Viterbi algorithm; Wires;

fLanguage

English

Journal_Title

Communications, IEEE Transactions on

Publisher

ieee

ISSN

0090-6778

Type

jour

DOI

10.1109/26.223789

Filename

223789