Title :
Gate-controlled junction breakdown in stored charge transistors
Abstract :
The gate-controlled junction breakdown has been observed in p-channel stored charge field-effect transistors which can be attributed to tunnel emission between the p+drain region and its inverted n+surface.
Keywords :
Breakdown voltage; Electric breakdown; Electrons; FETs; Fabrication; Insulation; Nonlinear equations; Polynomials; Resistors; Threshold voltage;
Journal_Title :
Proceedings of the IEEE
DOI :
10.1109/PROC.1972.8825
