Performance evaluation of microprocessor array

In the design of uniformly structured and tightly coupled multiple microprocessor/microcomputer systems, if each node is allowed to access certain portions of the memory in each of its neighbour nodes, bus contention may occur and an intelligent priority resolver must be incorporated to solve the contention problem effectively. A successful access is indicated by a successful handshake between the nodes concerned. The paper endeavours to evaluate the effects of these memory accesses under given request patterns, as well as under a stochastic model, assuming that all nodes are alike.