High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices

Author

Singh, N. ; Agarwal, A. ; Bera, L.K. ; Liow, T.Y. ; Yang, R. ; Rustagi, S.C. ; Tung, C.H. ; Kumar, R. ; Lo, G.Q. ; Balasubramanian, N. ; Kwong, D.-L.

Author_Institution

Inst. of Microelectron., Singapore, Singapore

Volume

27

Issue

5

fYear

2006

fDate

5/1/2006 12:00:00 AM

Firstpage

383

Lastpage

386

Abstract

This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10⁶. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA/μm were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.

Keywords

MOSFET; elemental semiconductors; nanowires; oxidation; phase shifting masks; silicon; silicon-on-insulator; 140 to 1000 nm; CMOS devices; GAA FET; Si; electrostatic control; electrostatic shielding; n-FET; p-FET; phase shift mask lithography; self-limiting oxidation techniques; silicon nanowire transistor; silicon-on-insulator; substrate bias; Electrostatics; FETs; Fabrication; FinFETs; Lithography; MOSFETs; Nanoscale devices; Oxidation; Silicon on insulator technology; Threshold voltage; CMOS-compatible process; gate-all-around (GAA); silicon nanowire transistor; surround gate; wrap-around-gate;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2006.873381

Filename

1626464