Title :
Observation of suppressed interface state relaxation under positive gate biasing of the ultrathin oxynitride gate p-MOSFET subjected to negative-bias temperature stressing
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore
fDate :
5/1/2006 12:00:00 AM
Abstract :
The impact of a positive gate relaxation voltage on the recovery of an ultrathin oxynitride gate p-MOSFET subjected to negative-bias temperature stressing is investigated. Apart from reaffirming previous observations on the accelerated threshold voltage recovery due primarily to positive field-induced discharge of positive SiO2 bulk states, the results also unambiguously show that the relaxation of Si/SiO2 interface states (Nit) is suppressed. The observed suppression of Nit relaxation poses an important challenge to the existing viewpoint of increased Nit relaxation under positive gate biasing.
Keywords :
MOSFET; elemental semiconductors; interface states; silicon; silicon compounds; stress relaxation; Si-SiO2; gate biasing; gate relaxation voltage; interface state relaxation; negative-bias temperature stressing; p-MOSFET; ultrathin oxynitride gate; Acceleration; Character generation; Degradation; Dielectric measurements; Interface states; MOSFET circuits; Plasma measurements; Stress measurement; Temperature; Threshold voltage; Charge pumping current; SiON; hole trapping; negative-bias temperature instability (NBTI); nitrided oxide; oxynitride;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2006.873878