Digital clock phase shifter without a phase locked loop

A digitally controlled clock phase shifter is described that avoids the use of conventional phase locked loops (PLLs) with their attendant stability problems. The hardware is suitable for implementation as part of an integrated circuit. Two implementations are discussed, one of which has low power consumption and is suitable for clocks of moderate speed and the second of which is suitable at higher frequencies. Simulation shows that the circuit is practically insensitive to component and timing tolerances. A prototype of the moderate speed version has been tested and has shown results comparable to simulation results