Title :
On the practical application of sequential code reduction (Corresp.)
Author :
Schmandt, Frederick D.
fDate :
7/1/1976 12:00:00 AM
Abstract :
Two approaches to reducing the number of modulo 2 adders in a sequential code reduction decoding circuit for a binary cyclic code are presented.
Keywords :
Cyclic codes; Decoding; Sequential decoding; Adders; Circuits; Decoding; Equations; Parity check codes; Polynomials; Testing; Upper bound;
Journal_Title :
Information Theory, IEEE Transactions on
DOI :
10.1109/TIT.1976.1055586
