DocumentCode
925472
Title
On the practical application of sequential code reduction (Corresp.)
Author
Schmandt, Frederick D.
Volume
22
Issue
4
fYear
1976
fDate
7/1/1976 12:00:00 AM
Firstpage
482
Lastpage
483
Abstract
Two approaches to reducing the number of modulo 2 adders in a sequential code reduction decoding circuit for a binary cyclic code are presented.
Keywords
Cyclic codes; Decoding; Sequential decoding; Adders; Circuits; Decoding; Equations; Parity check codes; Polynomials; Testing; Upper bound;
fLanguage
English
Journal_Title
Information Theory, IEEE Transactions on
Publisher
ieee
ISSN
0018-9448
Type
jour
DOI
10.1109/TIT.1976.1055586
Filename
1055586
Link To Document