Bipolar CMOS-merged technology for a high-speed 1-Mbit DRAM

Author

Kobayashi, Yutaka ; Asayama, Kyoichiro ; Oohhayashi, M. ; Hori, Ryoichi ; Kitsukawa, Goro ; Itoh, Kiyoo

Author_Institution

Hitachi Ltd., Ibaraki, Japan

Volume

36

Issue

4

fYear

1989

fDate

4/1/1989 12:00:00 AM

Firstpage

706

Lastpage

711

Abstract

A novel high-performance bipolar-CMOS (complementary metal oxide semiconductor) merged technology for a 1-Mb DRAM (dynamic random access memory) is proposed. A memory cell having a twenty-times-higher soft-error immunity (as compared to the conventional device) in its bit-line mode and a bipolar transistor having a high-drive ability (f_T=5.2 GHz at I_c=1.2 mA) can be realized. The fabrication process is fully compatible with the conventional CMOS DRAM and involves only three additional masking steps. An experimental 1-Mb BiCMOS (bipolar CMOS) DRAM was fabricated using this technology, with a typical access time of 32 ns

Keywords

CMOS integrated circuits; bipolar integrated circuits; integrated memory circuits; random-access storage; 1 Mbit; 1.2 mA; 32 ns; 5.2 GHz; DRAM; bipolar-CMOS; bit-line mode; high-drive ability; masking steps; merged technology; soft-error immunity; BiCMOS integrated circuits; Bipolar transistors; CMOS memory circuits; CMOS process; CMOS technology; Capacitance; Fabrication; Minimization; Paper technology; Random access memory;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.22475

Filename

22475