Title :
Q-modules: internally clocked delay-insensitive modules
Author :
Rosenberger, F.U. ; Molnar, C.E. ; Chaney, T.J. ; Fang, Ting-pien
Author_Institution :
Inst. for Biomed. Comput., Washington Univ., St. Louis, MO, USA
fDate :
9/1/1988 12:00:00 AM
Abstract :
Q-modules are internally clocked modules that can be used to satisfy delay-insensitive specifications. A single delay element is required with a one-sided bound that its value be greater than the maximum delay of the combination logic. Prototypes of components to implement Q-modules have been designed, and a design aid program, QSYN, to place instances of these components, personalize a PLA, and generate a MAGIC or CIF file for a CMOS realization, including the delay circuitry, is being developed. Testability is one of the advantages of Q-modules over clock-free delay-insensitive modules; circuitry is included in the cells for testing the logic and interconnections
Keywords :
CMOS integrated circuits; asynchronous sequential logic; integrated logic circuits; logic design; logic testing; sequential circuits; CMOS realization; Q-modules; QSYN; delay-insensitive; internally clocked; testability; testing; Assembly; CMOS logic circuits; Circuit synthesis; Circuit testing; Clocks; Delay; Flip-flops; Logic testing; Metastasis; Timing;
Journal_Title :
Computers, IEEE Transactions on
