Title :
n-user asynchronous arbiter
Author_Institution :
UniversitÃ\xa0 di Pisa, Dipartimento Sperimentale di, Elettrotecnica ed Elettronica, FacoltÃ\xa0 di Ingegneria, Pisa, Italy
Abstract :
A very simple asynchronous arbiter is given for n concurrent asynchronous processors interconnected in a speed-independent way. The arbiter, based on the 2-user perfect asynchronous arbiter of Patil, is structured in a modular way. At every processor, a module is given. The arbiter takes shape by properly interconnecting the modules.
Keywords :
computer architecture; parallel processing; computer architecture; concurrent asynchronous processors; n-user asynchronous arbiter; parallel processing;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19750001
