DocumentCode
926676
Title
Parallel architectures for computing cyclic convolutions
Author
Yeh, C.-S. ; Reed, I.S. ; Truong, T.K.
Author_Institution
University of Southern California, Department of Electrical Engineering, Los Angeles, USA
Volume
130
Issue
5
fYear
1983
fDate
8/1/1983 12:00:00 AM
Firstpage
409
Lastpage
416
Abstract
In the paper two parallel architectural structures are developed to compute one-dimensional cyclic convolutions. The first structure is based on the Chinese remainder theorem and Kung´s pipelined array. The second structure is a direct mapping from the mathematical definition of a cyclic convolution to a computational architecture. To compute a d-point cyclic convolution the first structure needs d/2 inner product cells, while the second structure and Kung´s linear array require d cells. However, to compute a cyclic convolution, the second structure requires less time than both the first structure and Kung´s linear array. Another application of the second structure is to multiply a Toeplitz matrix by a vector. A table is listed to compare these two structures and Kung´s linear array. Both structures are simple and regular and are therefore suitable for VLSI implementation.
Keywords
signal processing; Chinese remainder theorem; Kung linear array; Kung pipelined array; Toeplitz matrix; VLSI; cyclic convolutions; digital signal processing; vector;
fLanguage
English
Journal_Title
Communications, Radar and Signal Processing, IEE Proceedings F
Publisher
iet
ISSN
0143-7070
Type
jour
DOI
10.1049/ip-f-1.1983.0068
Filename
4645896
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