DocumentCode
926820
Title
A multilevel systolic approach for fuzzy inference hardware
Author
de Salvador, L. ; Gutierrez, J.
Author_Institution
Tech. Group on Hardware & Adv. Control, Nat. Inst. of Aerosp. Technol., Madrid, Spain
Volume
15
Issue
5
fYear
1995
Firstpage
61
Lastpage
71
Abstract
Our digital fuzzy processor´s main features are high throughput, performance independent of fuzzy-model size, high design parameter flexibility, Max-Min inference, and ability to handle a large number of complex rules without loss of efficiency. We carried out circuit development using a VHDL simulator, with European Silicon Structures´ 1-μm standard cells. We have achieved performance results of over 10-million fuzzy logical inferences per second.
Keywords
fuzzy control; hardware description languages; inference mechanisms; logic CAD; logic design; microprocessor chips; systolic arrays; uncertainty handling; Max-Min inference; VHDL simulator; circuit development; design parameter flexibility; digital fuzzy processor; fuzzy inference hardware; fuzzy logical inference; multilevel systolic approach; standard cells; Circuits; Control system synthesis; Costs; Fuzzy control; Fuzzy logic; Fuzzy systems; Hardware; Performance loss; Standards development; Throughput;
fLanguage
English
Journal_Title
Micro, IEEE
Publisher
ieee
ISSN
0272-1732
Type
jour
DOI
10.1109/40.464591
Filename
464591
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