DocumentCode :
926908
Title :
Billion-transistor architectures: there and back again
Author :
Burger, Doug ; Goodman, James R.
Author_Institution :
Texas Univ., Austin, TX, USA
Volume :
37
Issue :
3
fYear :
2004
fDate :
3/1/2004 12:00:00 AM
Firstpage :
22
Lastpage :
28
Abstract :
In September 1997, Computer published a special issue on billion-transistor microprocessor architectures. Comparing that issue´s predictions about the trends that would drive architectural development with the factors that subsequently emerged shows a greater-than-predicted emphasis on clock speed and an unforeseen importance of power constraints. Of seven architectural visions proposed in 1997, none has yet emerged as dominant. However, as we approach a microarchitectural bound on clock speed, the primary source of improved performance must come from increased concurrency. Future billion-transistor architectures will be judged by how efficiently they support distributed hardware without placing intractable demands on programmers.
Keywords :
parallel architectures; performance evaluation; power consumption; billion-transistor architectures; clock speed; concurrency; distributed hardware; microprocessor architectures; performance; power constraints; Application software; Clocks; Computer architecture; Conductivity; Delay; Hardware; Instruction sets; Out of order; Parallel processing; Wires;
fLanguage :
English
Journal_Title :
Computer
Publisher :
ieee
ISSN :
0018-9162
Type :
jour
DOI :
10.1109/MC.2004.1273999
Filename :
1273999
Link To Document :
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