High-Voltage-Tolerant Analog Circuits Design in Deep-Submicrometer CMOS Technologies

Author

Seo, Dongwon ; Dabag, Hayg ; Guo, Yuhua ; Mishra, Manu ; McAllister, Gene H.

Author_Institution

Qualcomm Inc., San Diego

Volume

54

Issue

10

fYear

2007

Firstpage

2159

Lastpage

2166

Abstract

Electrical stress-relieved analog circuit design techniques using only baseline devices are presented, 1-to-2 logic level shifter, optional diode insertion, and adaptive biasing scheme are introduced to meet a reliability guideline that ensures sufficient lifetime. The proposed idea was successfully demonstrated with 12-bit I/Q digital-to-analog converter (DAC) and an operational amplifier having a Classs-AB output stage in 65-nm n-well CMOS technology and a high temperature operating life (HTOL) test was performed to evaluate the reliability of the design.

Keywords

CMOS analogue integrated circuits; digital-analogue conversion; integrated circuit design; integrated circuit reliability; integrated circuit testing; operational amplifiers; Classs-AB output stage; DAC; HTOL test; adaptive biasing scheme; baseline devices; deep-submicrometer CMOS technologies; design reliability; digital-to-analog converter; diode insertion; electrical stress-relieved analog circuit design; high temperature operating life test; high-voltage-tolerant analog circuits design; operational amplifier; shifter; Analog circuits; CMOS analog integrated circuits; CMOS logic circuits; CMOS technology; Digital-analog conversion; Diodes; Guidelines; Logic circuits; Logic design; Logic devices; 1-to-2 logic level shifter; adaptive biasing scheme; diode insertion; electrical stress; high-voltage analog circuits;

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2007.904600

Filename

4346679