Systolic super summation with reduced hardware

A systolic super summer is a cellular apparatus for summing floating-point numbers. The apparatus receives floating-point summands, converting them to fixed-point within a sieve-like cellular array. The emerging fixed-point numbers are summed in a pipelined array of long accumulators. An improved design is presented for the summer´s sieve. Although the new sieve is structurally simpler and uses less hardware, the throughput per unit area is the same as that for the previously designed sieve. The new sieve´s architectural regularity makes it ideal for implementation in VLSI circuit technology