DocumentCode :
928249
Title :
On optimal single jog river routing [VLSI layout]
Author :
Tuan, Tai-Ching
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Oklahoma Univ., Norman, OK, USA
Volume :
41
Issue :
3
fYear :
1992
fDate :
3/1/1992 12:00:00 AM
Firstpage :
366
Lastpage :
369
Abstract :
The wiring problem of providing a planar rectilinear wire connection between two sets of terminals which lie on two horizontal lines in the plane is called the river routing. The problem has been widely studied. It is normally studied in conjunction with design variable(s) optimization problem. The author studies this problem when there is at most one horizontal segment in each wire. Efficient optimal algorithms are given for the following design variables: offset, separation, area, and shortest total wire length. The tight upper bound on the separation is also given
Keywords :
VLSI; circuit layout CAD; VLSI layout; area; design variable; offset; optimal algorithms; optimal single jog river routing; optimization; planar rectilinear wire connection; separation; shortest total wire length; tight upper bound; wiring problem; Algorithm design and analysis; Computer science; Design optimization; Pins; Rivers; Routing; Upper bound; Very large scale integration; Wire; Wiring;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/12.127451
Filename :
127451
Link To Document :
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