A high-speed and highly uniform submicrometer-gate BPLDD GaAs MESFET for GaAs LSIs

The authors present formation conditions for ion-implanted regions of a GaAs buried p-layer lightly doped drain (BPLDD) MESFET that can improve short-channel effect, V_th uniformity, and FET operating speed, simultaneously. For 0.7-μm gates, a Mg⁺ dose of 2×10¹² cm^-2 at 300 keV and a Si⁺ dose of 2×10¹² cm^-2 at 50 keV are suitable for the p layer and n´ layer, respectively. A σV _th of 7 mV is realized. Gate-edge capacitance of the 0.7-μm-gate BPLDD that consists of both overlap capacitance and fringing capacitance is successfully reduced to 0.5 fF/μm, which is about 50% of that of a non-LDD buried p-layer (BP) FET. Another parasitic capacitance due to the p-layer was found to have less effect on the speed than the gate-edge one. Consequently, the gate propagation delay time of the BPLDD can be reduced to 15 ps at power dissipation of 1 mW/gate, which is about 65% of that of a BP. Applying the 0.7-μm-gate BPLDD to 16-kb SRAMs, the authors have obtained a maximum access time of less than 5 ns with a galloping test pattern