DocumentCode :
928477
Title :
A pipelined adaptive differential vector quantizer for low-power speech coding applications
Author :
Shanbhag, Naresh R. ; Parhi, Keshab K.
Author_Institution :
Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
Volume :
40
Issue :
5
fYear :
1993
fDate :
5/1/1993 12:00:00 AM
Firstpage :
347
Lastpage :
349
Abstract :
A fine-grain pipelined adaptive differential vector quantizer architecture is proposed for low-power speech coding applications. The pipelined architecture is developed by employing the relaxed look-ahead technique. The hardware overhead due to pipelining is only the pipelining latches. Simulations with speech sampled at 8 kHz show that, for a vector dimension of 8, the degradation in the signal-to-noise ratio (SNR) due to pipelining is negligible. Furthermore, this degradation is independent of the level of pipelining. Thus the proposed architecture is attractive from an integrated circuit (IC) implementation point of view
Keywords :
parallel architectures; pipeline processing; speech coding; vector quantisation; 8 kHz; IC implementation; low-power speech coding; pipelined adaptive differential vector quantizer; pipelining latches; relaxed look-ahead technique; signal-to-noise ratio; Algorithm design and analysis; Circuits; Digital filters; Finite impulse response filter; Intersymbol interference; Nonlinear filters; Pipeline processing; Signal processing algorithms; Simulated annealing; Speech coding;
fLanguage :
English
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
Publisher :
ieee
ISSN :
1057-7130
Type :
jour
DOI :
10.1109/82.227377
Filename :
227377
Link To Document :
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