Parametric study of latchup immunity of deep trench-isolated, bulk, nonepitaxial CMOS

The improvement of latchup immunity in bulk, nonepitaxial CMOS with deep trench isolation has been demonstrated using numerical simulation. Through a proper design of trench dimensions and layout, it is shown that the holding voltage can be increased to a level above the power supply voltage (3.3 V in deep-submicrometer CMOS), yielding latchup-free CMOS even for nonepitaxial substrates. The holding voltage is strongly influenced by the current flow patterns in the conductivity-modulated well and substrate regions, which are affected by trench depth, layout parameters, and the tank and p⁺/n⁺ emitter doping concentrations. The deep trench makes the current flow patterns two-dimensional, and this causes parametric dependencies that cannot be explained from simple trench-isolation techniques. Design issues that are unique to deep trench isolation have been identified