An algorithm for the partitioning of logic circuits

The exhaustive testing of today´s digital circuits is not possible, owing to the vast test sequences which would have to be applied. Breaking down the circuit into manageable subcircuits (partitioning) makes exhaustive testing practicable. Partitioning has previously been done by the designer of the circuit in rather an ad hoc manner. The paper describes an algorithm which can be used to find the partitioning points in a circuit. The algorithm is illustrated for circuits containing reconvergent and nonreconvergent fan-outs.