DocumentCode :
928778
Title :
Programmable variable-rate up/down counter for generating binary logarithms
Author :
Lo, H.Y. ; Lu, J.H. ; Aoki, Y.
Author_Institution :
National Tsing Hua University, Department of Electrical Engineering, Hsinchu, Republic of China
Volume :
131
Issue :
4
fYear :
1984
fDate :
7/1/1984 12:00:00 AM
Firstpage :
125
Lastpage :
131
Abstract :
The design of an algorithm for a programmable variable-rate counter for generating precise binary logarithmic functions is presented. The error in log2(l + x), as defined by Iog2(l + x) ¿¿ x, may be considered as a set of straight lines whose slopes, either positive or negative, are chosen to be integral multiples of a binary fraction. By using a programmable counter whose rate is proportional to the slope of the line segments, the error is corrected. The circuitry is simple because no add operation is needed. The precision of the answer depends upon the number of bits used. In addition, an algorithm to synthesise the variable-rate up/down counter (VRU/DC), thus reducing the number of calculations, is given. It pinpoints the break points for this design, and also specifies the range covered by the segment for optimal precision. The algorithm can also be used to generate the antilogarithm.
Keywords :
counting circuits; digital arithmetic; antilogarithm generation; binary logarithms generation; error correction; optimal precision; programmable variable-rate up/down counter;
fLanguage :
English
Journal_Title :
Computers and Digital Techniques, IEE Proceedings E
Publisher :
iet
ISSN :
0143-7062
Type :
jour
DOI :
10.1049/ip-e.1984.0023
Filename :
4646112
Link To Document :
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