Traffic: a novel geometric algorithm for fast wire-optimized floorplanning

As the size and complexity of very large scale integrated (VLSI) circuits increase, the need for faster floorplanning algorithms also grows. This paper introduces trapezoidal floorplanning for integrated circuits (Traffic), a new method for creating wire- and area-optimized floorplans. Through the use of connectivity grouping, simple geometry, and a constrained brute-force approach, Traffic achieves an average of 18% lower wire estimate than simulated annealing (SA) in orders of magnitude less time. This speed allows designers to rapidly explore a large circuit design space, to evaluate small changes to big circuits, to fit bounding boxes, and to produce initial solutions for other floorplanning algorithms