Three-dimensional place and route for FPGAs

Author

Ababei, Cristinel ; Mogal, H. ; Bazargan, Kia

Author_Institution

Electr. & Comput. Eng. Dept., Univ. of Minnesota, Minneapolis, MN

Volume

25

Issue

6

fYear

2006

fDate

6/1/2006 12:00:00 AM

Firstpage

1132

Lastpage

1140

Abstract

We present timing-driven partitioning and simulated-annealing (SA)-based placement algorithms together with a detailed routing tool for three-dimensional (3-D) field-programmable gate array (FPGA) integration. The circuit is first divided into layers with a limited number of interlayer vias, and then placed on individual layers, while minimizing the delay of critical paths. We use our tool as a platform to explore the potential benefits, in terms of delay and wire length (WL), that 3-D technologies can offer for FPGA fabrics. Experimental results show, on average, a total decrease of 25% in WL and 35% in delay can be achieved over traditional two-dimensional chips, when ten layers are used in 3-D integration

Keywords

field programmable gate arrays; network routing; simulated annealing; timing circuits; 3D field-programmable gate array integration; FPGA; critical paths; delay; interlayer vias; routing tool; simulated-annealing-based placement algorithm; timing-driven partitioning; wire length; Circuits; Delay; Fabrics; Field programmable gate arrays; Minimization; Partitioning algorithms; Routing; Signal design; Time to market; Wire; Field-programmable gate arrays (FPGAs); routing; three-dimensional (3-D) circuits; timing-driven placement;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/TCAD.2005.855945

Filename

1629145