A high-precision VLSI winner-take-all circuit for self-organizing neural networks

Author

Choi, Joongho ; Sheu, Bing J.

Author_Institution

Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA

Volume

28

Issue

5

fYear

1993

fDate

5/1/1993 12:00:00 AM

Firstpage

576

Lastpage

584

Abstract

The design and implementation of a high-precision VLSI winner-take-all (WTA) circuit that can be arranged to process 1024 inputs are presented. The cascade configuration can be used to significantly increase the competition resolution and maintain high-speed operation for a large-scale network. The total bias current increases in proportion to the number of circuit cells so that a nearly constant response time is achieved. A unique dynamic current steering method is used to ensure that only a single winner exits in the final output. Experimental results for a prototype chip fabricated in a 2-μm CMOS technology show that a cell can be a winner if its input is larger than those of the other cells by 15 mV. The measured response time is around 50 ns at a 1-pF load capacitance. This analog winner-take-all circuit is a key module in the competitive layer of self-organizing neural networks

Keywords

CMOS integrated circuits; VLSI; neural chips; self-organising feature maps; 1 pF; 2 micron; 50 ns; CMOS technology; VLSI winner-take-all circuit; WTA circuits; cascade configuration; constant response time; dynamic current steering; high-speed operation; large-scale network; prototype chip; self-organizing neural networks; total bias current; CMOS technology; Capacitance measurement; Circuits; Delay; Large-scale systems; Neural networks; Prototypes; Semiconductor device measurement; Time measurement; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.229397

Filename

229397