DocumentCode :
928896
Title :
Power partition and emitter size optimization for bipolar ECL circuit
Author :
Hsieh, Hsueh Y. ; Chin, Kenneth ; Chuang, Ching-Te
Author_Institution :
IBM, Hopewell Junction, NY, USA
Volume :
28
Issue :
5
fYear :
1993
fDate :
5/1/1993 12:00:00 AM
Firstpage :
548
Lastpage :
552
Abstract :
An automated approach for optimizing the performance of a bipolar ECL circuit is described. A quadratic equation representing an approximate surface is used to express the circuit delay in terms of the power partition and current densities in the current-switch and emitter-follower stages. During the iteration of the optimization process, the optimum obtained from each approximate surface is used as the nominal point for the next iteration. As the nominal point converges to the optimal, the approximate surface converges to a section of the real optimum surface. This methodology transforms the circuit optimization into a multivariable optimization problem and is shown to provide an optimum design with circuit analysis accuracy. The design considerations for high-performance ECL circuits are also discussed
Keywords :
bipolar integrated circuits; emitter-coupled logic; integrated logic circuits; logic CAD; optimisation; automated approach; bipolar ECL circuit; circuit delay; current densities; current-switch; emitter size optimization; emitter-follower stages; multivariable optimization problem; power partition; quadratic equation; CMOS technology; Circuit analysis; Circuit optimization; Circuit simulation; Circuit testing; Current density; Delay; Design optimization; Equations; Switches;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/4.229401
Filename :
229401
Link To Document :
بازگشت